Archimedes objective: a high-level CPU emulation with low-level emulated support components. At least as a first step.

Additionally cleans up several compiler warnings for CI platforms.

Included ARM fixes:

• only the lowest byte of a register affects shift-by-register quantities;
• a 0-size immediate rotation that sets carry copies the highest bit of the value [not] being rotated;
• flags are set properly for R15 destination data processing operations;
• LDR to an address register with writeback prefers the value read to the writeback;
• exceptions and BL include status bits in the value placed into R14;
• exceptions retain the proper mode in the value placed into R14 ad pick an appropriate PC offset based on the exception type*;
• block writes handle decrementing addresses properly, use the load PSR flag for user-register selection during STM and properly handle write back versus registers included in the transfer list (including not conflating registers of the same number from different modes).

* since I'm trying to maintain an implementation separation between my version of ARM operations and any specific ARM implementation I want this to be codified separately rather than flowing naturally from the ARM2's pipeline.